sdram_ctrl_int.vhd


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;

library UNISIM;
use UNISIM.VComponents.all;

library work;
use work.types.all;


entity sdram_ctrl_int is end sdram_ctrl_int;



architecture behavioral of sdram_ctrl_int is begin end Behavioral;