ee_data_int.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.types.all;
entity ee_data_int is
port(
CLK: in std_logic;
AS_RESET: in std_logic;
EE_READ_REQ: in std_logic;
EE_ACK: out std_logic;
EE_DATA: out std_logic_vector(EE_DATA_MSB downto 0);
EE_WRITE_REQ_RE: in std_logic;
EE_INT_REQ: out std_logic;
EE_ADDR_OFFSET: out std_logic_vector(DATA_IN_ADDRESS_MSB downto 0);
EE_INT_ACK: in std_logic;
EE_INT_DATA: in std_logic_vector(15 downto 0)
);
end ee_data_int;
architecture Behavioral of ee_data_int is
signal ee_addr_offset_i: std_logic_vector(DATA_IN_ADDRESS_MSB downto 0);
signal ee_read_req1: std_logic;
signal ee_read_req2: std_logic;
signal ee_int_ack_old: std_logic;
begin
end Behavioral;