sdram_ctrl_int.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
library UNISIM;
use UNISIM.VComponents.all;
library work;
use work.types.all;
entity sdram_ctrl_int is
generic(
SDRAM_ADDR_WIDTH: integer:= 25;
FAKE_ADDR_WIDTH: integer:= 10
);
port(
CLK: in std_logic;
AS_RESET: in std_logic;
EE_INT_REQ: in std_logic;
EE_DATA_TR_ACK: buffer std_logic;
EE_DATA: out std_logic_vector(EE_INT_DATA_MSB downto 0);
EE_ADDRESS: in std_logic_vector(PACKET_ADDRESS_MSB downto 0);
EE_ADDR_OFFSET: in std_logic_vector(DATA_IN_ADDRESS_MSB downto 0);
HFE_INT_REQ: in std_logic;
HFE_DATA_TR: out std_logic;
HFE_DATA_TR_ACK: in std_logic;
HFE_INT_FIFO_DATA: in std_logic_vector(HFE_INT_DATA_MSB downto 0);
WFIFO_FULL: out std_logic;
DDR_BUSY: in std_logic;
DDR_REQ: in std_logic;
DDR_ACK: out std_logic;
DDR_ADDR_IN: out std_logic_vector(SDRAM_ADDR_WIDTH - 1 downto 0);
DDR_WRITE_EN: out std_logic;
DDR_VALID_IN: out std_logic;
DDR_CMD_BUSY: in std_logic;
DDR_DATA_IN: out std_logic_vector(127 downto 0);
DDR_DATA_IN_VLD: out std_logic;
DDR_DATA_BUSY: in std_logic;
DDR_DATA_OUT: in std_logic_vector(127 downto 0);
DDR_DATA_OUT_VLD: in std_logic;
DDR_DATA_OUT_NEXT: out std_logic
);
end sdram_ctrl_int;
architecture behavioral of sdram_ctrl_int is
signal ee_trans_end: std_logic;
signal ee_trans_en: std_logic;
type t_states is(FSM_idle, FSM_wait, FSM_wait_cmd, FSM_wait_data, FSM_hfe_req, FSM_hfe_trans, FSM_ee_req, FSM_ee_trans);
signal cur_state: t_states;
signal next_state: t_states;
signal hfe_data_tr_ack_re: std_logic;
signal hfe_data_tr_ack_fe: std_logic;
signal hfe_data_tr_ack_reg: std_logic;
signal reg_hfe_data: std_logic_vector(127 downto 0);
signal reg_hfe_data_ce: std_logic_vector(3 downto 0);
signal reg_hfe_addr: std_logic_vector(SDRAM_ADDR_WIDTH - 1 downto 0);
signal cnt_hfe_out: std_logic_vector(1 downto 0);
signal cnt_hfe_en: std_logic;
signal reg_hfe_out: std_logic;
signal ee_int_req_re: std_logic;
signal ee_int_req_reg: std_logic;
signal reg_ee_data: std_logic_vector(127 downto 0);
signal ee_addr: std_logic_vector(SDRAM_ADDR_WIDTH - 1 downto 0);
signal ee_addr_valid: std_logic;
signal ddr_load: std_logic;
signal cnt_ee_out: std_logic_vector(2 downto 0);
signal cnt_ee_out_reg: std_logic;
signal cnt_ee_of: std_logic;
signal cnt_ee_full: std_logic;
signal ee_sec_run: std_logic_vector(0 downto 0);
signal ddr_read: std_logic;
begin
process(CLK, AS_RESET)
begin
end process;
process(cur_state, HFE_INT_REQ, HFE_DATA_TR_ACK, DDR_REQ, DDR_BUSY, EE_INT_REQ, DDR_DATA_OUT_VLD, ee_trans_end, DDR_DATA_BUSY, DDR_CMD_BUSY)
begin
end process;
process(cur_state, HFE_INT_REQ, HFE_DATA_TR_ACK, DDR_REQ, DDR_BUSY, EE_INT_REQ, DDR_DATA_OUT_VLD, ee_trans_end, DDR_DATA_BUSY, DDR_CMD_BUSY)
begin
end process;
process(CLK, AS_RESET)
begin
end process;
process(CLK, AS_RESET)
begin
end process;
process(cnt_hfe_out)
begin
case cnt_hfe_out is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
end process;
process(CLK, AS_RESET)
begin
end process;
hfe_reg: for i in 0 to(128 / 32) - 1 generate
end generate;
DDR_DATA_IN_VLD <= reg_hfe_out;
DDR_DATA_IN <= reg_hfe_data;
process(CLK, AS_RESET)
begin
end process;
process(CLK, AS_RESET)
begin
end process;
hfe_data_tr_ack_re <= HFE_DATA_TR_ACK and not hfe_data_tr_ack_reg;
hfe_data_tr_ack_fe <= not HFE_DATA_TR_ACK and hfe_data_tr_ack_reg;
process(CLK, AS_RESET)
begin
end process;
process(CLK, AS_RESET)
begin
end process;
process(cnt_ee_out)
begin
end process;
process(cnt_ee_out)
begin
end process;
DDR_DATA_OUT_NEXT <= cnt_ee_full;
process(cnt_ee_out, AS_RESET)
begin
end process;
process(CLK, AS_RESET)
begin
end process;
ee_trans_end <= cnt_ee_full and ee_sec_run(0);
ee_reg: for i in 0 to(128 / 16) - 1 generate
ee_reg1: if i = 0 generate
end generate;
ee_reg2: if i /= 0 generate
end generate;
end generate;
EE_DATA <= reg_ee_data(127 downto(127 + 1) - 16);
process(CLK, AS_RESET)
begin
end process;
process(EE_ADDRESS, EE_ADDR_OFFSET)
begin
end process;
process(CLK, AS_RESET)
begin
end process;
ee_int_req_re <= EE_INT_REQ and not ee_int_req_reg;
process(CLK, AS_RESET)
begin
end process;
process(ddr_read, reg_hfe_addr, ee_addr)
begin
end process;
process(ddr_read, hfe_data_tr_ack_fe, ee_addr_valid)
begin
end process;
end Behavioral;