ee_data_int.vhd

port(
CLK: in std_logic;
AS_RESET: in std_logic;
EE_READ_REQ: in std_logic;
EE_ACK: out std_logic;
EE_DATA: out std_logic_vector(EE_DATA_MSB downto 0);
EE_WRITE_REQ_RE: in std_logic;
EE_INT_REQ: out std_logic;
EE_ADDR_OFFSET: out std_logic_vector(DATA_IN_ADDRESS_MSB downto 0);
EE_INT_ACK: in std_logic;
EE_INT_DATA: in std_logic_vector(15 downto 0)
);

signal ee_addr_offset_i: std_logic_vector(DATA_IN_ADDRESS_MSB downto 0);
signal ee_read_req1: std_logic;
signal ee_read_req2: std_logic;
signal ee_int_ack_old: std_logic;

process(CLK, AS_RESET)
begin
if AS_RESET = '1' then
ee_read_req1 <= '0';

elsif CLK = '1' and CLK'event then
ee_read_req1 <= EE_READ_REQ;

end if;

end process;

process(CLK, AS_RESET)
begin
if AS_RESET = '1' then
ee_read_req2 <= '0';

elsif CLK = '1' and CLK'event then
ee_read_req2 <= ee_read_req1;

end if;

end process;

process(CLK, AS_RESET)
begin
if AS_RESET = '1' then
ee_addr_offset_i <= (others => '0');

elsif CLK = '1' and CLK'event then
if EE_WRITE_REQ_RE = '1' then
ee_addr_offset_i <= (others => '0');

elsif ee_int_ack = '1' and ee_int_ack_old = '0' then
ee_addr_offset_i <= ee_addr_offset_i + 1;

end if;

end if;

end process;
EE_ADDR_OFFSET <= ee_addr_offset_i;

process(CLK, AS_RESET)
begin
if AS_RESET = '1' then
EE_INT_REQ <= '0';

elsif CLK = '1' and CLK'event then
if ee_int_ack = '1' then
EE_INT_REQ <= '0';

elsif ee_read_req2 = '1' then
EE_INT_REQ <= '1';

end if;

end if;

end process;

process(CLK, AS_RESET)
begin
if AS_RESET = '1' then
ee_int_ack_old <= '0';

elsif CLK = '1' and CLK'event then
ee_int_ack_old <= ee_int_ack;

end if;

end process;
EE_ACK <= EE_INT_ACK;
EE_DATA <= EE_INT_DATA;