\chapter{Seznam použitých zkratek}


\begin{description}
   \item[2D] Two-Dimensional
   \item[AIS] Alarm Indication Signal
   \item[ANSI] American National Standards Institute
   \item[APS] Automatic Protection Switch
   \item[ASIC] Application-specific Integrated Circuit
   \item[ATM] Asynchronous Transfer Mode
   \item[AU] Administrative Unit
   \item[BIP] Bit Interleaved Parity
   \item[CD] Carrier Detection
   \item[CPU] Central Processing Unit
   \item[CRC] Cyclic Redundancy Check
   \item[DCCM] Data Communication Channel Multiplex Section
   \item[DCCR] Data Communication Channel Regenerator Section
   \item[DCM] Digital Clock Manager
   \item[DS] Digital Signal
   \item[EDIF] Electronic Design Interchange Format
   \item[EEPROM] Electrically Erasable Programmable Read-Only Memory
   \item[EOP] End Of Packet
   \item[FCS] Frame Check Sequence
   \item[FIFO] First In First Out
   \item[FL] Frame link
   \item[FPGA] Field Programmable Gate Array
   \item[FSM] Finite State Machine
   \item[GFP] Generic Framing Procedure
   \item[HDLC] High-level Data Link Control
   \item[CHAP] Challenge-Handshake Authentication Protocol
   \item[IDS] Intrusion Detection System
   \item[IEEE] Institute of Electrical and Electronics Engineers
   \item[IFC] Interface
   \item[IP] Internet Protocol
   \item[IPX] Internetwork Packet Exchange
   \item[ISDN] Integrated Services Digital Network
   \item[ITU-T] International Telecommunication Union - Telecommunication
   \item[LCP] Link Control Protocol
   \item[LL] Local link
   \item[LOF] Loss Of Frame
   \item[LOH] Line overhead
   \item[LOS] Loss of Signal
   \item[LVDS] Low Voltage Differential Signal
   \item[LVPECL] Low Voltage Positive Emitter Coupled Logic
   \item[LVP] Low Volume traffic Protocols
   \item[MIT] Massachusetts Institute of Technology
   \item[MRU] Maximum Receive Unit
   \item[MSOH] Multiplex Section Overhead
   \item[MS] Multiplex Section
   \item[NCP] Network Control Protocol
   \item[NLP] Network-Layer Protocol
   \item[OC] Optical Carrier
   \item[OOF] Out Of Frame
   \item[OSI] Open Systems Interconnection
   \item[PAP] Password Authentication Procedure
   \item[PaR] Place and Route
   \item[PBGA] Plastic Ball Grid Array
   \item[PCB] Printed Circuit Board
   \item[PCI] Peripheral Component Interconnect
   \item[POH] Path Overhead
   \item[POS] Packet Over SONET
   \item[POS-PHY] Packet over SONET - Physical layer Protocol
   \item[PPP] Point to Point Protocol
   \item[RDI] Remote Defect Indication
   \item[REI] Remote Error Indication
   \item[RFC] Request For Comments
   \item[RJ] Registered Jack
   \item[RPR] Resilient Packet Rings
   \item[RSOH] Regenerator Section Overhead
   \item[RTS] Ready To Sent
   \item[RX] Receive
   \item[SCAMPI] Scaleable Monitoring Platform for the Internet
   \item[SDH] Synchronous Digital Hierarchy
   \item[SFP] Small Form-Factor Pluggable
   \item[SOH] Section Overhead
   \item[SONET] Synchronous Optical Network
   \item[SOP] Start of Packet
   \item[SPE] Synchronous Payload Envelope
   \item[SSRAM] Synchronous Static Random Access Memory
   \item[STM] Synchronous Transport Module
   \item[STS] Synchronous Transport Signal
   \item[SW] Software
   \item[TBGA] Tape Ball Grid Array
   \item[TOH] Transport Overhead
   \item[TX] Transmit
   \item[UUT] Unit Under Test
   \item[VHDL] VHSIC (very high speed integrated circuits) hardware description language
   \item[VT] Virtual Tributaries
   \item[VC] Virtual Container
   \item[XAPP] Xilinx Application Note
   \item[XFP] 10 Gigabit Small Form Factor Pluggable
\end{description}
